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| DLBM-CA120/121 DLBM-CA120 (16Kbit EEPROM) DLBM-CA121 (64Kbit EEPROM) TM Bluetooth Module Class 2 A Class 2 Bluetooth module suitable for wireless Audio applications. 1.FEATURES: Suitable for Headset, MP3... applications. Reducing the size and thickness greatly using high-density packaging technology. High sensitivity to achieve better performance. Compliant to various interfaces: UART, USB, PIO... Wide operating temperature range: -30~+80J . 2.Device diagram Figure 1. DLBM-CA120/CA121 Block Diagram Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 3.General Specification Bluetooth TM Specification Frequency Modulation Transmission rate Receive sensitivity Maximum output power Operating Voltage Operating temperature Antenna Impedance Package size Talk time (Audio application) Stand-by time (Audio application) * Base on application circuit figure 7* Version 1.1 2402~2480MHz FHSS/GFSK 721kbps -83dBm +4dBm(Class 2) 1.8V or 2.2~3.6V -30~+80J 50 ohm 9.1*7.9*1.5mm *Up to 4.5 hours (120mA Battery) *Up to 200 hours (120mA Battery) 4.Rating Min Storage Temperature VDD_1.8V VDD_IO VREG_IN -40 -0.4 -0.4 -0.4 Max +150 +1.9 +3.6 +4.2 Unit J V V V Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 5.Recommended Operating conditions Min Guaranteed RF performance range VDD_1.8V VDD_IO VREG_IN +1.7 +2.7 +2.2 +1.9 +3.6 +4.2 V V V -10 Max +70 Unit J 6.Interface Interface Antenna UART Interface SPI Interface PIO Interface Description External Antenna 50 ohm TX,RX,RTS,CTS(9600bps~1.5Mbps) Synchronous Serial Interface for firmware download 9 terminals Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 7.Power Supply Diagram ANT VDD_1.8V BPF Balun EEPROM BC2-Audio VDD_IO VREG_IN X'tal Figure 2. Power Supply Diagram Terminal VDD_1.8V VDD_IO VREG_IN VDD=3.0V NC 2.7 to 3.6V 2.7 to 3.6V VDD=1.8V 1.7 to 1.9V 2.7 to 3.6V NC 8.RF Characteristics Operating Condition: +25J , VDD=1.8V Min. Typ. Max. Unit MHz dBm dBm dBm dBm dBm April 20, 2005 Proprietary Information and Specifications are Subject to Change RF Characteristics 1. Fequency Range 2. Output Power 3. Sensitivity at 0.1% BER 1) 2402MHz 2) 2441MHz 3) 2480MHz 4. Maximum Input Level (BERO 0.1%) 2400 ~ 2483.5 -6 1.5 4 -70 -70 -70 -20 -83 -83 -83 0 Data Sheet DLBM-CA120/121 5. Adjacent channel selectivity 1) C/I F=F0 + 1MHz 2) C/I F=F0 - 1MHz 3) C/I F=F0 + 2MHz 4) C/I F=F0 - 2MHz 5) C/I FU 6) C/I FO F0 + 3MHz F0 - 5MHz -4 -4 -35 -21 -45 -45 -18 -35 -55 0 0 -30 -20 dB dB dB dB dB dB 7) C/I F=FImage 6. Adjacent channel transmit power 1) F=F0 O 2) F=F0 O 2MHz 3MHz -9 -20 -40 dB dBc dBc 7. Modulation Characteristics 1) Modulation G f1avg 2) Modulation G f2max 8. Initial Carrier Frequency Tolerance 1) 2402MHz 2) 2441MHz 3) 2480MHz 9. Carrier Frequency Drift 1) 1slot 2) 5slot 4) Drift rate 10. 20dB Bandwidth for modulated carrier 1) 2402MHz 2) 2441MHz 3) 2480MHz 11.C/I co - channel 140 115 -75 -75 -75 -20 -25 -20 165 155 -12 -11 -10 9 10 6.5 879 816 819 9 175 kHz kHz 75 75 75 20 25 20 1000 1000 1000 11 kHz kHz kHz kHz kHz KHz/50us KHz KHz KHz dB Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 9.Audio Codec The DLBM-CA120 CODEC is compatible with the direct speaker drive and microphone input using a minimum number of external components. It is primarily intended for voice applications and it is fully operational from a single 1.8 Volt power supply. A fully differential architecture has been implemented for optimal power supply rejection and low noise performance. The digital format is 15-bit/sample linear PCM with a data rate of 8kHz. The CODEC has an input stage containing a microphone amplifier, variable gain amplifier and aU -G ADC. Its output stage contains a DAC, low-pass filter and output amplifier. The CODEC functional diagram is shown below: MIC_P Input Ampler G U -ADC MIC_N Digital Circulty SPKR_P SPKR_N Re Output Ampler DAC Figure 3. DLBM-CA120 CODEC Diagram 10. Input Stage A low noise variable gain amplifier amplifies the signal difference between inputs MIC_N and MIC_P. The input may be from either a microphone or line. The amplified signal is then digitised by aU -G ADC. The high frequency single bit output from the ADC is converted to 15-bit 8kHz linear PCM data. The gain is programmable via a PSKEY and has a 42dB range with 3dB resolution. At maximum gain the full scale input level is 3mV rms. A bias network is required for operation Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 with a microphone whereas the line input may be simply a.c. coupled. The following sections explain each of these modes. Single ended signals are supported by DLBM-CA120: a single ended signal may be driven into either MIC_N or MIC_P with the undriven input coupled to ground by a capacitor. At the maximum gain the signal to noise ratio is better than 60dB and distortion is better than -75dB relative to a full-scale sine wave. At lower gain settings (such as used for line input) the signal to noise ratio improves to better than -75dB. 11. Microphone Input The DLBM-CA120 CODEC has been designed for use with microphones that have sensitivities between -60 and -40dBV. The sensitivity of -60dBV is equivalent to a microphone output of 1g A when presented with an input level of 94dB SPL and loaded with 1k[ . The microphone should be biased as shown: V bias C1 MIC_P RL C2 MIC MIC_N Input Ampler Figure 4. DLBM-CA120 Microphone Biasing The input impedance at MIC_N and MIC_P is typically 20k[ . C1 and C2 should be 47nF. RL sets the microphone load impedance and is normally between 1 and 2k[ . V bias should be chosen to suit the microphone and have sufficient low noise. It may be obtained by filtering the output of a PIO line. Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 12. Line Input If the input gain is set to less than 21dB DLBM-CA120 automatically selects line input mode. In this mode the input impedance at MIC_N and MIC_P is increased to 130k[ typical. At the minimum gain setting the maximum input signal level is 380 mV rms. Figures 5 show two circuits for line input operation and show connections for either differential or single ended inputs. C1 MIC_P DLBM-CA120 C2 MIC_N C1 MIC_P DLBM-CA120 C2 MIC_N Figure 5. Single-ended Microphone Input Note: C1 and C2 should be 15nF. Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 13.Output Stage The digital data is converted to an analogue value by a DAC, then it is filtered prior to amplification by the output amplifier and it is available as a differential signal between SPKR_P and SPKR_N. the output amplifier is capable of driving a speaker directly if its impedance is greater than or equal to 8[ . The amplifier is stable with capacitive loads up to 500pF. The gain is programmable with a range of 21dB and a resolution of 3dB. Maximum output level is typically 700 mV rms for high impedance loads, or 20mA rms for low impedance loads. The signal to noise is better than 70dB and the distortion is less than -75dB. SPKR_P SPKR_N Figure 6. Speaker Output Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 14.Reference design for Headset application Figure 7. Headset application circuit ***Important: The circuit is offered without warranty and Delta is unable to accept any liability for direct or consequential loss associated with their use. It is therefore important for designers to ensure that their Bluetooth headset design is properly evaluated in a Design Verification Test. The results of the Design Verification Test should be used to assess the suitability of the headset for manufacture.*** Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 15. RECOMMENDED REFLOW PROFILE The temperature rise to 150J for preliminary heating shall be made for 30 seconds or longer The preliminary heating shall be done at the temperature of 160J+ 10J for 60 ~ 90 seconds. The heating shall be at the temperature of 200J or higher For 20 ~ 40 seconds and the peak temperature shall be 230J+ 5J Figure 8. REFLOW PROFILE Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 16.Pin description Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data Sheet Name PIO_11 PIO_9 SP+ SPMIC+ MICGnd Gnd Gnd ANT AIO_0 Gnd Gnd Gnd Vdd_1.8V VREG_IN Refer to Power supply diagram Refer to Power supply diagram April 20, 2005 Proprietary Information and Specifications are Subject to Change RF input/output Programmable input/output Description Programmable I/O terminal Programmable I/O terminal Speaker output positive Speaker output negative Microphone input positive Microphone input negative DLBM-CA120/121 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 VDD_IO USB_DN USB_DP UART_TX UART_RX UART_CTS UART_RTS Reset_B PIO_4 PIO_5 PIO_10 PIO_3 Gnd Gnd Gnd PIO_2 PIO_1 PIO_0 SPI_MOSI Programmable input/output line Programmable input/output line Programmable input/output line Serial Peripheral Interface data input Refer to Power supply diagram USB data minus USB data plus with selectable internal 1.5kohm pull-up resistor UART data output active high UART data input active high UART clear to send active low UART request to send active low Reset if low Programmable input/output line Programmable input/output line Programmable input/output line Programmable input/output line Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 36 37 38 SPI_MISO SPI_CLK SPI_CSB Serial Peripheral Interface data output Serial Peripheral Interface clock Chip select for Serial Peripheral Interface, active low Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 17.Dimensions (mm) A B C D 9.10.2 7.90.2 O 1.50.2 O 0.45O0.15 E F G H 0.35O0.15 0.8O0.1 0.4O0.1 0.4O0.1 I J K M 0.8O0.1 0.8O0.1 0.3O0.1 0.7O0.1 N 0.40.1 O Figure 9. Output pin dimensions Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 18. Layout Guide Don't place the ground on the top layer (Inside area) Figure 10. Land Pattern Unit: mm DLBM-C**2* T5mil Ground VIA Main Ground plant Side View Figure 11. Layout Example Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change DLBM-CA120/121 19. Record of changes Date Dec 16, 2004' Reason of change 1) Update application circuit 2) Create DLBM-CA121 64K EEPROM version 3) Includes SPI pin definition Dec 30, 2004' Jan 17, 2005' April 20, 2005' May 20, 2005' Application circuit upgrade. (Low current consumption Emerson Shih version) General Specification & Layout Guide correction Includes pin dimension tolerance Change dimensions tolerance 1) DG 0.4O 0.1 0.45O 0.15 2) EG 0.4O 0.1 0.35O 0.15 Emerson Shih Ming Wu Leo Chuang Engineer Emerson Shih Contact information: Website: http://www.deltaww.com Email: Richard.meng@delta.com.tw Tel No.: 886-3-3591968#2930 Data Sheet April 20, 2005 Proprietary Information and Specifications are Subject to Change |
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